Moore FSM: A sequence detector

This project was a complete Moore finite state machine sequence detector for ECE2277A. The circuit reads one input bit at a time, turns the output on after detecting a target four-bit sequence, and keeps that output high until a second four-bit sequence turns it back off.

The interesting part was not only making the detector function. The assignment required two state-assignment strategies, Boolean simplification, gate-cost comparison, a structural implementation in Quartus, and a simulation waveform that proved the selected design behaved correctly.

I started by mapping the detector into states that represented how much of the current sequence had already been matched. Because the output in a Moore FSM depends on state instead of the immediate input, the state diagram had to carry both progress through the bit pattern and whether the output should be active.

From there, I built a state table with current state, next state for x = 0 and x = 1, and output z. This made the design easier to reason about before touching gates: every transition had a clear purpose, and every output value could be traced back to a named state.

I compared a guideline-based state assignment against a Gray-code assignment. The goal was to keep related states adjacent where it helped reduce the final logic, then use Karnaugh maps to derive the D flip-flop input equations and output equation.

The selected implementation used three D flip-flops and simplified sum-of-products equations for Q1+, Q2+, Q3+, and z. After counting the required gates and gate inputs, the guideline-based assignment came out as the cleaner and lower-cost option, so that became the circuit I implemented.

The final circuit was implemented structurally in Quartus with D flip-flops, AND gates, OR gates, and inverters. I kept the logic organized around the derived equations so the schematic stayed readable and each signal could be debugged from input x through the next-state logic.

Verification came through waveform simulation. The test sequence stepped through the expected states on clock edges, then drove z high only after the valid pattern was received. That simulation was the bridge between the handwritten logic work and the FPGA implementation.

This project made digital logic feel less abstract. A small change in state assignment could affect the amount of hardware needed, and the cleanest design was the one that stayed traceable from state diagram to truth table to K-map to schematic.

It also gave me practice communicating engineering tradeoffs. The final answer was not just a working detector; it was a reasoned choice between two implementations, backed by cost analysis and verified through simulation.